ASIM team
LIP6 Laboratory
Paris, France
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Contents
Document overview
Scope
Contacts
Applicable documents
Abbreviations
PCI-DDC overview
Function
Definitions and Principles
PCI-bus
HSL-network
Direct Deposit StateLess Receiver Protocol (DDSLRP)
Memory address
Message
Page
List of Pages to Emit (LPE)
Page descriptor
Message Identifier (MI)
Packet
Message reconstruction
FIFO queues
PCI-DDC notification
The remote write primitive
Principle
Message types
Error detection
PCI-DDC programming
Configuration registers
Register access modes
Register map
Device and Vendor Identification
Standard Status and Command Register
Status
Command
Class Code
Miscellaneous Functions
Device Requirement
PCI-DDC Status Register
PCI-DDC normal events
PCI-DDC error event
internal status
RCUBE status
PCI-DDC Status Mask Register
PCI-DDC normal event status mask
PCI-DDC error event status mask
RCUBE status mask
PCI-DDC Command
Received Message Identifier
LPE Management Registers
LMI Management Registers
LRM Base Address
RCUBE configuration
Structures in main memory
Page Descriptor in the LPE
Message Descriptor in the LMI
Received Message Descriptor in the LRM
PCI transactions
Packet Formats
PCI-DDC initialization
PCI-DDC pins
Overview
PCI Address and Data bus
PCI control signals
PCI special signals
Network IN/OUT ports
Configuration and status ports
PCI-DDC test mode
Supply
Pinout
Features
Manufacturer
Environment conditions / temperature range
Flexibility and expandability
Interchangeability
Power dissipation
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$Date: 1998/02/14 17:06:25 $
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