Register access modes

ASIM team
LIP6 Laboratory
Paris, France

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Register access modes

Registers are 32-bit wide but maybe split in fields. Each field has an independent access mode:
$\begin{mydescription} \itemsep -.8ex \item[(R)] Register may be read, and write... ...\ Write a 0 does not change the field, write a 1 clears it.\end{mydescription}$
Access to an undefined register, read a W type register or write a R type register does not matter. In that cases, write has no effect and read give an undefined value back. In the following description, set a bit means write 1, reset a bit means writes 0, moreover test if a bit is on means compare at 1.

Next: Register map Up: Configuration registers Previous: Configuration registers