FIFO queues

ASIM team
LIP6 Laboratory
Paris, France

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FIFO queues

PCI-DDC embeds FIFO queues (one per direction) in order to cope with the clock speed difference between the RCUBE router and PCI-bus.

When PCI-DDC emits data from the PCI-bus to RCUBE, until transmitting FIFO queue is not full, PCI-DDC can absorb the speed difference. Whenever the PCI-bus data throughput is lower than the RCUBE data throughput, the queue is not useful, since it cannot be filled. But whenever the PCI-bus data throughput is bigger than the RCUBE data throughput, the FIFO queue size defines the packet length, since the packet ends as soon as the queues is filled. The bigger the FIFO queue, the better throughput difference will be absorb. The transmitting FIFO queue size is 200 bytes.

When PCI-DDC receives data from RCUBE, receiving FIFO queue allows PCI-DDC to quickly flush the network, and to have enough time to ask for the bus. Furthermore, PCI-DDC can receive several messages from several senders at the same time, and so the receiving FIFO queue must be bigger than the transmitting one. The receiving FIFO queue size is 400 bytes.

Actually, those queue sizes could be discussed. They depend on lots of parameters such as message size, page size, time to obtain the PCI-bus, and so on. However, thoses sizes are a good tradeoff between silicon area and speed.

Next: PCI-DDC notification Up: Definitions and Principles Previous: Message reconstruction