PCI-DDC error event status mask

ASIM team
LIP6 Laboratory
Paris, France

Next: RCUBE status mask Up: PCI-DDC Status Mask Register Previous: PCI-DDC normal event status

PCI-DDC error event status mask

$\begin{mydescription} \item[Exceptional End of Packet Error Mask]~\ Should be ... ...k] Should be 1. When 0, the End of Packet Error is ignored.\end{mydescription}$

33(R/W) Page Transmitted Mask
32(R/W) Message Received Mask
&&&&&&24(R/W) Exceptional End of Packet Error Mask
&&&&&&23(R/W) CRC Header Error Mask
&&&&&&22(R/W) CRC Data Error Mask
&&&&&&21(R/W) End of Packet Error Mask
&&&&&&19(R/W) Timeout Error Mask
&&&&&&18(R/W) R3 Status Error Mask
&&&&&&17(R/W) Page Transmitted Overflow Mask
&&&&&&16(R/W) Message Received Overflow Mask
&&&&&&15(R/W) Sent Packet Overflow Mask
&&&&&&14(R/W) Received Packet Overflow Mask
&&&&&&13(R/W) Illegal LRM Access Mask
&&&&&&12(R/W) LMI Overflow Mask
&&&&&&&&&&9(R/W) R3 Status Mask
&&&&&&&&&&
§-19.5pt &&&&&&&&&&
44h 10106Reserved 1111111111111111 111111114Reserved 1010101010101010
&31&30&&&&&&&23&22&21&20&19&18&17&16&15&14&13&12&&&&&7&6&5&4&3&2&1&0&
8 Normal Status Masks 16 Error Status Masks 8 R3 Status Masks & PCI-DDC Status
$\begin{mydescription} \item[Timeout Error Mask] Should be 1. When 0, the Timeo... ...low Mask] Should be 1. When 0, the LMI Overflow is ignored.\end{mydescription}$

Next: RCUBE status mask Up: PCI-DDC Status Mask Register Previous: PCI-DDC normal event status