LMI Management Registers

ASIM team
LIP6 Laboratory
Paris, France

Next: LRM Base Address Up: Configuration registers Previous: LPE Management Registers

LMI Management Registers

Each received message having the LMI enable bit set (see Page Descriptors page ) is reported in the List of Message Identifier. This software queue contains one Message Descriptor for each received message that is completed.

The LMI is a circular queue which needs four pointers : one to the Base address, one to the Maximum address, one pointer to the Current received message, and one to the New received message. All those pointers are physical addresses. Each element in the LMI is 16 bytes length, the four lowest bits are 0. The maximum is harwired to maximum memory address in order to not cause an overflow error just after reset event.

33(R/W) Maximum Address

§-19.5pt
60h 28FFFF FFFh40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LMI Current Address

§-19.5pt
64h 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LMI New Address

§-19.5pt
68h 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LMI Base Address

§-19.5pt
6Ch 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&
LMI Registers
$\begin{mydescription} \item[LMI Maximum Address] That is the highest Message De... .... This register has to be set at the PCI-DDC initialization.\end{mydescription}$
At initialization phase, when those registers must to be set, the Bus Master bit (PCI command register) must be disasserted in order to avoid PCI-DDC start to receive a message from the network. The figure below highlights the address register usage.

60h14LMI Maximum Address10h2-- -- $\rightarrow$ 15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
17 Incremented by PCI-DDC 15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&
$\uparrow$ &&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
68h14LMI New Address10h2-- -- $\rightarrow$ 15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15Message Descriptor 3
17 Incremented by software 15Message Descriptor 2
&&&&&&&&
$\uparrow$ &&&&&&&&&15Message Descriptor 1
64h14LMI Current Address10h2-- -- $\rightarrow$ 15Message Descriptor 0
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
6Ch14LMI Base Address10h2-- -- $\rightarrow$ 15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/

15 PCI-DDC registers &&15 LMI in main memory
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& LMI management The Current Address is incremented by the software once it has read the Message Descriptor 0 to 3. PCI-DDC will write the new Message Descriptor at LMI New Address. When, New Address reaches the Current Address, it means the LMI is full and PCI-DDC must wait for the software to free space.

Next: LRM Base Address Up: Configuration registers Previous: LPE Management Registers