PCI-DDC initialization

PCI-DDC initialization is quite complex since the software must not only configure PCI-DDC but can initialize the RCUBE routing tables (See RCUBE specification for details).

RCUBE needs to have its NRESET pin low to be configured. It is therefore necessary to control this pin from PCI-DDC (R3 init register).
The second difficulty is start the throughput control between PCI-DDC and RCUBE. It is therefore necessary to begin independently PCI-DDC transmission module (TX init register), PCI-DDC reception module (RX init register) and RCUBE (R3 init register).
The third difficulty is to forbid PCI-DDC transmission while initialization is not completed, therefore Bus Master bit set ends.

The procedure begins with the RST_N signal assertion or, what is equivalent, by writing one in the Soft Reset register (see PCI-DDC command register). As soon as the RST_N signal is disasserted or one cycle after the Soft Reset register set, PCI-DDC is ready to be configured.

The result of the reset action is:

flush the FIFO queues,
set an idle state in the finite state machines,
set default values in the configuration registers,
reset (means switch off) RCUBE (R3 init to 0) and the PCI-DDC communication modules (TX init and RX init to 0).

Then, the starting procedure is:

configure RCUBE routing tables ;
configure all PCI-DDC registers, except for R3 init, TX init, RX init, and Bus Master ;
switch on TX module, set TX init ;
switch on RCUBE, set R3 init ;
switch on RX module, set RX init ;
allows PCI-DDC to become master, set Bus Master.

12pt

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