ASIM team LIP6 Laboratory Paris, France

LPE Management Registers     

All remote-write request are placed by the PCI-DDC driver in a software queue, called the List of Pages to Emit (LPE). This list resides in main memory, it is written by the processor and it is read by PCI-DDC. It contains actually Page Descriptors presented page . The pages are transmitted in the queue order.

The LPE is a circular queue which needs four pointers : one to the Base address, one to the Maximum address, one to the Current transmitted page and one to the New page to transmit. All those pointers are physical addresses. Since a Page Descriptor is 16 bytes length, the four lowest bits are 0.

33(R/W) Maximum Address

§-19.5pt
50h 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LPE Current Address

§-19.5pt
54h 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LPE New Address

§-19.5pt
58h 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&

33(R/W) LPE Base Address

§-19.5pt
5Ch 280000 000h40 0 0 0
&31&&&&&&&&&&&&&&&&&&&&&&&&&&&4&&&&
LPE Registers

At initialization phase, when those registers are set, the Bus Master bit (PCI command register) must be disasserted in order to avoid PCI-DDC to start a Page Descriptor read. When the PCI-DDC driver wants to add one or several Page Descriptors into the LPE, it must:

• read the LPE registers to check if there is enough space.
• Write the Page Descriptors in the LPE.
• Write the New Address in PCI-DDC.

The figure below highlights the address register usage.

50h14LPE Maximum Address10h2-- -- $\rightarrow$ 15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
17 Incremented by software  15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&
$\uparrow$&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
58h14LPE New Address10h2-- -- $\rightarrow$ 15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15Page Descriptor 3
17 Incremented by PCI-DDC  15Page Descriptor 2
&&&&&&&&
$\uparrow$&&&&&&&&&15Page Descriptor 1
54h14LPE Current Address10h2-- -- $\rightarrow$ 15Page Descriptor 0
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´/
&&&&&&&&&&&&&&&&&15 ´´´´´´´´´´´´´´´´´´´´´´´´´´´´/
5Ch14LPE Base Address10h2-- -- $\rightarrow$ 15´´´´´´´´´´´´´´´´´´´´´´´´´´´´/

15 PCI-DDC registers &&15 LPE in main memory 
&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& LPE management The New Address has been incremented after the addition of the Page Descriptors 0 to 3. Then PCI-DDC knowns that it has to transmit pages beginning by 0 up to 3. When Current Address reaches the New Address, it means that PCI-DDC has no more page to transmit.

Server design A. Fenyö mpc@mpc.lip6.fr - contact people About this Web Site $Date: 1998/02/14 17:06:25 $

Copyright © 1997-1998 UPMC/LIP6 All rights reserved