PCI-DDC Status Register

ASIM team
LIP6 Laboratory
Paris, France

Next: PCI-DDC normal events Up: Configuration registers Previous: Device Requirement

PCI-DDC Status Register

This register reports the normal events (ie: Message Received bit and Page Transmitted bit) and error events, it is the PCI-DDC status. There is a mask bit for each status bit. If a mask is 1, as soon as the associated event happens then the INTA# signal is asserted, else the mask is 0 then the event is ignored. If it is an error event (except for R3 Status Error) then the Bus Master bit (PCI command register) is reset and PCI-DDC waits for a configuration transaction (for example to read the PCI-DDC Status Register and restarts PCI-DDC). PCI-DDC does not stop after a normal event or R3 Status Error. In the following description, we suppose that every event can be hidden by its associated mask.

33(R/C) Page Transmitted
32(R/C) Message Received
31(R/C) More than 4096 Page Transmitted
30(R/C) More than 256 Page Transmitted
29(R/C) More than 16 Page Transmitted
28(R/C) More than 4096 Page Received
27(R/C) More than 256 Page Received
26(R/C) More than 16 Page Received
24(R/C) Exceptional End of Packet Error
23(R/C) CRC Header Error
22(R/C) CRC Data Error
21(R/C) End of Packet Error
19(R/C) Timeout Error
18(R/C) R3 Status Error
17(R/C) Page Transmitted Overflow
16(R/C) Message Received Overflow
15(R/C) Sent Packet Overflow
14(R/C) Received Packet Overflow
13(R/C) Illegal LRM Access
12(R/C) LMI Overflow
&10(R) Transaction Number
&&&9(R) R3 Status
&&&
§-19.5pt &&&
40h 1010101010101010 1010101010101010 101010101 33 1010101010101010
&31&30&29&28&27&26&25&24&23&22&21&20&19&18&17&16 &15&14&13&12&&11&&8&7&6&5&4&3&2&1&0&
8 Normal Events 16 Error Events 8 R3 Events & PCI-DDC Status

Next: PCI-DDC normal events Up: Configuration registers Previous: Device Requirement