Test pins

.25

test: 3.3v / 5v IN
When high, all the functional registers of R3P, but not the configuration registers, are chained in a scanpath.
scanin: 3.3v / 5v IN
Input of the test scanpath of R3P.
scanout: 3.3v OUT
Output of the test scanpath of R3P.
test_smi: 3.3v / 5v IN
When high, the registers of the SMIs clocked by the clock ckin are chained in a scanpath.
scanin_smi: 3.3v / 5v IN
Input of the test scanpath of the SMIs.
scanout_smi: 3.3v OUT
Output of the test scanpath of the SMIs.
test_hsl: 3.3v / 5v IN
When low, this signal allows the scanning of each register of the HSLs.
scanin_hsl: 3.3v / 5v IN
Input of the test scanpath of the HSls.
scanout_hsl: 3.3v OUT
Ouput of the test scanpath of the HSLs.
zctest: 3.3v / 5v IN
When low, this signal enables the scanning of each register of the ZC block through a dedicated test scanpath.
zcscin: 3.3v / 5v IN
Input of the test scanpath of the ZC block.
zcscout: 3.3v OUT
Output of the test scanpath of the ZC block.
ckm1, ckm2: 3.3v / 5v IN
The HSLs and ZC scanpathes use a biphase clocking scheme (different from the main clock) (fig. 3.6). These clocks can be software drived and don't need to be free running.
loop_par(7:0): 3.3v / 5v IN
For test consideration, each SMI implements a parallel loop back mechanism (fig. 3.1). When high, the signal loop_par enables a connection between the parallel output of a port and its parallel output. This signal must be set while nreset is active.
loop_ser(7:0): 3.3v / 5v IN
Each HSL implements a serial loop back mechanism that enables an internal direct connection between its serial output and its serial input (fig.3.1). When low, the signal loop_ser[7:0] activates this internal serial loop back in the HSL 7..0. This signal must be set while nreset is active.

**Figure 3.1:** Loop back modes

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