ASIM team LIP6 Laboratory Paris, France

Timing

 

Figure 3.2: Clockconfig timing 

 

symbol parameters min max

t_clockconfig clockconfig period 12 ns -

twh_clockconfig clockconfig high width 5 ns -

twl_clockconfig clockconfig low width 5 ns -

tr_clockconfig clockconfig edge rise time 1 ns -

tf_clockconfig clockconfig edge fall time 1 ns -

tsu_scaninconfig set-up time of scaninconfig[8:0] 1 ns -

th_scaninconfig hold time of scaninconfig[8:0] 3 ns -

t_{scanoutconfig} clockconfig falling edge to scanoutconfig - 5 ns

 

Figure 3.3: Fifo write strobe  

 

symbol parameters min max

tw_strobe datastrobe period 12 ns

tw1_strobe width datastrobe high 5 ns

tw0_strobe width datasrobe low 5 ns

tsu_datafifo set-up time of datain[8:0] 0 ns

th_datafifo hold time of datain[8:0] 3 ns

 

Figure 3.4: Input signals timing  

 

symbol parameters min max

t_ckin ckin period 12 ns 18 ns

twh_ckin ckin high width 5 ns 8 ns

twl_ckin ckin low width 5 ns 8 ns

tr_ckin ckin edge rise time 1 ns 3 ns

tf_ckin ckin edge fall time 1 ns 3 ns

tsu_fccreceived set-up time of fccreceived0,1 6 ns

th_fccreceived hold time of fccreceived0,1 0 ns

tsu_test set-up time of test 25 ns

th_test hold time of test 0 ns

tsu_scanin set-up time of scanin 5 ns

th_scanin hold time of scanin 1 ns

tsu set-up time of test_smi 10 ns

th hold time of test_smi 0 ns

tsu set-up time of scanin_smi 5 ns

th hold time of scanin_smi 1 ns

 

Figure 3.5: Output signals timing  

 

symbol parameters min max

t_ckin ckin period 12 ns 18 ns

twh_ckin ckin high width 5 ns 8 ns

twl_ckin ckin low width 5 ns 8 ns

tr_ckin ckin edge rise time 1 ns 3 ns

tf_ckin ckin edge fall time 1 ns 3 ns

t_do ckin falling edge to dataout0,1 8 ns

t_sd ckin falling edge to senddata0,1 8 ns

t_scout ckin falling edge to scanout 6 ns

t_lkst ckin falling edge to linkstatus[7:0] 5.5 ns

t_sfcc ckin falling edge to sendfcc0,1 6 ns

t_scoutsmi ckin falling edge to scanout_smi 5 ns

 

Figure 3.6: HSL test timing 

 

symbol parameters min max

tTCK test_hsl stable to ckm1 100 ns -

tW1 width ckm1 high 10 ns -

td12 ckm1 falling edge to ckm2 rising edge 10 ns -

tW2 width ckm2 high 10 ns -

td21 ckm2 falling edge to ckm1 rising edge 10 ns -

tSU data setup time(scanin to ckm1 falling edge) 10 ns -

tH data hold time(ckm1 falling edge to scanin change) 10 ns -

tR ckm2 rising edge to scanout - 10 ns

tCKT ckm2 to test_hsl change 100 -

 

Figure 3.7: ZC block test timing 

 

symbol parameters min max

tTCK zctest stable to ckm1 100 ns -

tW1 width ckm1 high 10 ns -

td12 ckm1 falling edge to ckm2 rising edge 10 ns -

tW2 width ckm2 high 10 ns -

td21 ckm2 falling edge to ckm1 rising edge 10 ns -

tSU data setup time(zcscin to ckm1 falling edge) 10 ns -

tH data hold time(ckm1 falling edge to zcscin change) 10 ns -

tR ckm2 rising edge to zcscout - 10 ns

tCKT ckm2 to zctest change 100 -

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