LIP6 Laboratory
Paris, France
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ASIM team
LIP6 Laboratory Paris, France |
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The informations given hereafter specify for each signal name, its direction IN (for input) or OUT (for output) as well as the high level voltage that can be applied on input buffer or delivered by output buffer.
RCUBE uses an internal 80 MHz clock externally provided by the board.
When low, this signal synchronously resets on the falling edge of ckin, the serial links and all the R3S functional registers except the configuration registers. The signal nreset must be active at least for 10 ckin clock cycles to insure the minimal reset period of both the HSL links and the ZC block.
When this signal remains at low level for at least 100 ns, it asynchronously forces the serial link into an uncalibrated state. When the signal raises, the serial link enters a boot phase (unless nreset is active while the clock ckin is running).
When this signal is forced at low level for at least 100 ns, it asynchronously initializes the ZC registers contents. It must be active whenever nreset is active.
Link 0...7 input serial data.
Link 0...7 output serial data.
When low, this signal reinitializes the deserializer part of the serial link7..0. These signal are used only with optical fiber link. If copper links are used, these signal must always be forced at a high level.
When high, this signal indicates that the HS link is calibrated.
These pins must be connected through a 100 ohm resistor.
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