Latency vs. Bandwidth Trade-Off

ASIM team
LIP6 Laboratory
Paris, France

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Latency vs. Bandwidth Trade-Off

Many different communications protocols can be implemented in firmware on the SmartHSL board. Among other things, firmware code writer should be quite careful about HSL flow control management. The simple, byte based, flow control (If the reception FIFO is not empty, then pop a data, if the emission FIFO is not full, then push a data) is very inefficient from the point of view of the throughput. It requires conditional branch which implies DSP pipeline stall states.

Since the HSL datapath FIFO status can be observed from the DSP, it is easy to use a larger granulatity flow control (If the reception FIFO level is above 64, then the DSP can pop 64 data words without any other test). This solution is evidently better from the bandwidth use point of view, but it generates latency.

The expected bandwidth for 64 word bursts is about 50 MB/s per processor.

Next: Conclusion and Industrial Opportunities Up: SmartHSL Architecture and Expected Previous: Data Pathes