Data Pathes

ASIM team
LIP6 Laboratory
Paris, France

Next: Latency vs. Bandwidth Trade-Off Up: SmartHSL Architecture and Expected Previous: SmartHSL Architecture and Expected

Data Pathes

The PCI Bus peak bandwidth is 132 MB/s. The observed maximum bandwidth is actually between 80 MB/s and 100 MB/s, depending on data transaction type and PCI bridge quality.

The system bus of the DSP is 24 bit wide. Only 16 bits are used to and from the network FIFOs. Accesses to these FIFOs are made with 1 wait-state at 66 MHz. Assuming no other external accesses are made (to external RAM, ROM, or Control chips), by the internal DSP DMA engines, the efficient bandwidth on this bus is 66 MB/s, half-duplex.

The router uses a 80 MHz clock, and is able to import and export one byte per cycle. Time multiplex and demultiplex between the FIFO (16 bits) and the router (8 bits) is ensured by the FIFO/RCube PLD Interface. Thus, the bandwidth on this datapath is 80 MB/s, full-duplex. The same PLD is also responsible of flow control credit management.

In this design, the bottle-neck can be either the DSP System bus (66 MB/s, half duplex) or the DSP computing power, depending of firmware code optimization.

Next: Latency vs. Bandwidth Trade-Off Up: SmartHSL Architecture and Expected Previous: SmartHSL Architecture and Expected