Internal architecture

ASIM team
LIP6 Laboratory
Paris, France

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Internal architecture

The PCI-DDC internal (Fig 3) structure consists of finite state machines and FIFOs. The actual PCI bus throughput is 132Mbytes/sec. The HSL throughput is 80Mbytes/sec for each direction. In order to solve the throughput mismatch, PCI-DDC has two FIFOs (one for each direction).

**Figure 3:** PCI-DDC Internal Structure
$\begin{figure} \center\leavevmode \psfig {file=pciddc_a.eps,width=.75\textwidth}\end{figure}$

When PCI-DDC emits data from the PCI-bus to RCUBE, it can absorb the speed difference until TX FIFO is full. Whenever the PCI-bus data throughput is larger than the RCUBE throughput, the TX FIFO size defines the packet length, since the packet is cut as soon as the FIFO is full. When PCI-DDC receives data from the HSL network, the RX FIFO allows PCI-DDC to quickly flush the network. Each FIFO contains 400 bytes.

The configuration bloc manages all configuration registers, such as LPE, LMI and LRM pointers. It also contains registers to initialize and monitor the RCUBE router. The reception bloc (RX) extracts packets from the RX FIFO, checks CRC, performs DMA write for data, manages the LRM and LMI structures. This bloc contains a small cache to keep the last packet number and message identifier in order to save LRM access (if the current received packet belongs to the same message as the previous one, it is not necessary to perform LRM access since informations are already there). The transmission bloc (TX) reads LPE descriptor as soon as software move LPE pointers, performs DMA read for data and builds packets. It adds CRC and takes charge of data alignment if local address and remote address are not aligned on the same byte number. At last, the arbiter grants RX and TX blocs permission to request the PCI bus. This arbiter may be tune to favour either RX or TX.

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