3.PIN DESCRIPTION

Figure 2.1: Block description
4|l|FUNCTIONAL PINS

Pin name I/O Active level Brief Description

ckin I - Externally provided clock.

nreset I low Chip reset.

nreset_link[7:0] I low Serial link reset.

zcreset I low Impedance adaptator ZC reset.

sdin0 I - Link 0 serial data in.

sdin1 I - Link 1 serial data in.

sdin2 I - Link 2 serial data in.

sdin3 I - Link 3 serial data in.

sdin4 I - Link 4 serial data in.

sdin5 I - Link 5 serial data in.

sdin6 I - Link 6 serial data in.

sdin7 I - Link 7 serial data in.

sdout0 O - Link 0 serial data out.

sdout1 O - Link 1 serial data out.

sdout2 O - Link 2 serial data out.

sdout3 O - Link 3 serial data out.

sdout4 O - Link 4 serial data out.

sdout5 O - Link 5 serial data out.

sdout6 O - Link 6 serial data out.

sdout7 O - Link 7 serial data out.

recal0 I low Link0 deserializer reset.

recal1 I low Link1 deserializer reset.

recal2 I low Link2 deserializer reset.

recal3 I low Link3 deserializer reset.

recal4 I low Link4 deserializer reset.

recal5 I low Link5 deserializer reset.

recal6 I low Link6 deserializer reset.

4|l|CONFIGURATION PINS

clockconfig I - Configuration strobe.

scaninconfig [7:0] I - Input of the 8-bits parallel configuration port.

scanoutconfig [7:0] O - Output of the 8-bits parallel configuration port.

**Figure 2.1:** Block description
4\|l\|FUNCTIONAL PINS
Pin name	I/O	Active level	Brief Description
ckin	I	-	Externally provided clock.
nreset	I	low	Chip reset.
nreset_link[7:0]	I	low	Serial link reset.
zcreset	I	low	Impedance adaptator ZC reset.
sdin0	I	-	Link 0 serial data in.
sdin1	I	-	Link 1 serial data in.
sdin2	I	-	Link 2 serial data in.
sdin3	I	-	Link 3 serial data in.
sdin4	I	-	Link 4 serial data in.
sdin5	I	-	Link 5 serial data in.
sdin6	I	-	Link 6 serial data in.
sdin7	I	-	Link 7 serial data in.
sdout0	O	-	Link 0 serial data out.
sdout1	O	-	Link 1 serial data out.
sdout2	O	-	Link 2 serial data out.
sdout3	O	-	Link 3 serial data out.
sdout4	O	-	Link 4 serial data out.
sdout5	O	-	Link 5 serial data out.
sdout6	O	-	Link 6 serial data out.
sdout7	O	-	Link 7 serial data out.
recal0	I	low	Link0 deserializer reset.
recal1	I	low	Link1 deserializer reset.
recal2	I	low	Link2 deserializer reset.
recal3	I	low	Link3 deserializer reset.
recal4	I	low	Link4 deserializer reset.
recal5	I	low	Link5 deserializer reset.
recal6	I	low	Link6 deserializer reset.
4\|l\|CONFIGURATION PINS
clockconfig	I	-	Configuration strobe.
scaninconfig [7:0]	I	-	Input of the 8-bits parallel configuration port.
scanoutconfig [7:0]	O	-	Output of the 8-bits parallel configuration port.

4|l|PARALLEL PORTS : port 0 and port 1

Pin name I/O Active level Brief Description

datastrobe0 I - write strobe of the input asynchronous fifo.

datain0[8:0] I - incoming character on parallel port 0.

fccreceived0 I high adds a flit to the emission credit of the port 0.

sendfcc0 O high Port 0 can receive a flit.

senddata0 O high Data sending flag.

dataout0[8:0] O - outgoing character from parallel port 0.

muxps0 I high selects the parallel input on link 0.

datastrobe1 I - write strobe of the input asynchronous fifo.

datain1[8:0] I - incoming character on parallel port 1.

fccreceived1 I high adds a flit to the emission credit of the port 1.

sendfcc1 O high Port 1 can receive a flit.

senddata1 O high Data sending flag.

dataout1[8:0] O - outgoing character from parallel port 1.

muxps1 I high selects the parallel input on link 1.

4\|l\|PARALLEL PORTS : port 0 and port 1
Pin name	I/O	Active level	Brief Description
datastrobe0	I	-	write strobe of the input asynchronous fifo.
datain0[8:0]	I	-	incoming character on parallel port 0.
fccreceived0	I	high	adds a flit to the emission credit of the port 0.
sendfcc0	O	high	Port 0 can receive a flit.
senddata0	O	high	Data sending flag.
dataout0[8:0]	O	-	outgoing character from parallel port 0.
muxps0	I	high	selects the parallel input on link 0.
datastrobe1	I	-	write strobe of the input asynchronous fifo.
datain1[8:0]	I	-	incoming character on parallel port 1.
fccreceived1	I	high	adds a flit to the emission credit of the port 1.
sendfcc1	O	high	Port 1 can receive a flit.
senddata1	O	high	Data sending flag.
dataout1[8:0]	O	-	outgoing character from parallel port 1.
muxps1	I	high	selects the parallel input on link 1.

4|l|TEST PINS

Pin name I/O Active level Brief Description

test I high All the functional registers of R3P are controlable and observable through a scanpath. The clock used in test mode is the functional clock ckin.

scanin I - R3P Scanpath input.

scanout O - R3P Scanpath output.

test_smi I high The functional registers of the SMIs clocked by the clock ckin are controlable and observable through a scanpath. The clock used in test mode is the functional clock ckin.

scanin_smi I - SMIs Scanpath input.

scanout_smi O - SMIs Scanpath output.

test_hsl I low enables the scanning of each register of the HSLs through a test scanpath.

scanin_hsl I - input of the test scanpath of the HSLs.

scanout_hsl O - output of the test scanpath of the HSLs.

zctest I low enables the scanning of each register of the ZC block through a dedicated test scanpath.

zcscin I - input of the ZC test scanpath.

zcscout O - output of the ZC test scanpath.

loop_par[7:0] I high enables a direct connection between the output and the input of the SMIs before entering the HSLs.

loop_ser[7:0] I low enables an internal loop back between the serial output and the serial input of each HSL.

ckm1,ckm2 I - HSLs, ZC block test clocks.

zin,zou I - must be externally connected via a 100 ohm resistor.

4\|l\|TEST PINS
Pin name	I/O	Active level	Brief Description
test	I	high	All the functional registers of R3P are controlable and observable through a scanpath. The clock used in test mode is the functional clock ckin.
scanin	I	-	R3P Scanpath input.
scanout	O	-	R3P Scanpath output.
test_smi	I	high	The functional registers of the SMIs clocked by the clock ckin are controlable and observable through a scanpath. The clock used in test mode is the functional clock ckin.
scanin_smi	I	-	SMIs Scanpath input.
scanout_smi	O	-	SMIs Scanpath output.
test_hsl	I	low	enables the scanning of each register of the HSLs through a test scanpath.
scanin_hsl	I	-	input of the test scanpath of the HSLs.
scanout_hsl	O	-	output of the test scanpath of the HSLs.
zctest	I	low	enables the scanning of each register of the ZC block through a dedicated test scanpath.
zcscin	I	-	input of the ZC test scanpath.
zcscout	O	-	output of the ZC test scanpath.
loop_par[7:0]	I	high	enables a direct connection between the output and the input of the SMIs before entering the HSLs.
loop_ser[7:0]	I	low	enables an internal loop back between the serial output and the serial input of each HSL.
ckm1,ckm2	I	-	HSLs, ZC block test clocks.
zin,zou	I	-	must be externally connected via a 100 ohm resistor.

TOTAL: 138 pins

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