PCI Access

ASIM team
LIP6 Laboratory
Paris, France

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PCI Access

The PCI Bus (32 bits, 33 MHz) offers both bandwidth and system independence. The DSP56301 [4] provides an integrated PCI controller. Since this port supports full speed data transfers, the bandwidth on the PCI bus is limited by the Host CPU Bridge quality, and/or by the firmware running on the DSP.

As a rule, any master transaction can be initiated by the DSP, using dedicated registers specified in the DSP56301 data sheet. I/O or memory spaces can be targeted, by any transaction type (Read, Read Line, Read Multiple, Write, Write Line, Write and Invalidate). Though, transaction exceptions (Disconnect, Abort, Time Out) must be handled and recovered by software

As a slave, SmartHSL is mapped as a 64 KB window in the PCI memory space. All read or write PCI accesses in this window are handled by the DSP as pop or push in two 32 bit wide FIFOs. Those FIFOs are mapped as pseudo registers in the DSP address space.

Next: Network Access Up: SmartHSL Features Previous: Overview