Introduction

The High Speed Link (HSL) technology has been developed in the framework of the OMI-HIC ESPRIT project. It is a one Gigabit/sec, bidirectional, asynchronous, point to point, highly integrated serial link, fully compliant with the IEEE 1355 standard. An Association[4] exists to support and enhance the use of this standard. The RCUBE component is a dynamic router, implementing a wormhole strategy for low latency. It contains an 8*8 non-blocking cross-bar, and 8 HSLs. This VLSI component can be used to build high performance, scalable and low-cost interconnection networks. Since the internal router latency becomes 150 ns, the global network latency is negligible versus the software latency. Classical communication protocols, such as TCP/IP introduce multiple copies of data, resulting in high latency and low throughput. This is not acceptable for high speed networks such as HSL networks.

The PCI-DDC component presented here connects the RCUBE router to the PCI local bus. It implements the ``Direct Deposit State Less Receiver'' (DDSLR[3]) protocol, for efficient point to point communication, without any intermediate copies, and without processor overhead. The basic primitive is the remote write: PCI-DDC directly fetches data from local memory and write them into remote memory. PCI-DDC is a master on the PCI bus. It makes DMA and does not need processor help during the transfer. Figure 1 shows a typical architecture based on the PCI-DDC/RCUBE chip set.

**Figure 1:** Parallel Computer using PCI-DDC/RCUBE chip-set
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PCI-DDC offers 3 kinds of message: standard (any length) for data transfer, short (8-byte data) dedicated to signaling or monitoring, and composed (without data) to realize synchronization barriers. It manages data structures which describe the messages, it automatically splits the messages up in packets, it adds CRCs, it takes charge the byte realignment and it can inform whenever messages are left or arrived. It is able to operate at full PCI speed (up to 33MHz) and HSL speed (up to 80MHz). The main features of PCI-DDC are the following:

Low cost:: A single chip is enough to connect the PCI-local bus and the RCUBE router. It integrates all the required FIFOs and Finite State Machines, and uses the host memory processor to store its working data structures. This allows to design a simple add-in card. Furthermore, a single kind of add-in card is enough to build up an HSL network.
Performance:: The remote write primitive allows the system designer to implement very efficient message passing protocols from user memory to user memory without any copy by the system. It is so possible to use the HSL speed to the full.
Interoperable:: The PCI-DDC/RCUBE chip-set can be used with any processor providing a PCI-local bus, i.e. with Pentium, Alpha and PowerPC.

The PCI-DDC component has been designed at UPMC in the framework of the HPCN-EUROPRO (High Performance Computing and Networking) Esprit project[5]. Its goal is to build an high speed communication network for an heterogeneous parallel computer dedicated for both signal and data processing. It is based on PowerPC and Shark DSP VME boards. PCI-DDC will be also used at UPMC for the MPC[6] project, that is an high performance yet low cost server based on standard Pentium mother board interconnected by an HSL network.

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